Nintendo Switch BGA Pad Damage Analyzer

Nintendo Switch BGA Pad Damage AnalyzerLPDDR4 / LPDDR4X 200-ball

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Verdict

Intact

Nothing marked yet.

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Hover (or tap) any ball to read it here.
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This package

Hotkeys

1Inspect2Pad ripped3Jumpered 4Bridged5Flag0Erase RFit whole chipMMirror viewQ ERotate + −Zoom (or Ctrl + wheel)LLabels FFullscreen (whole app)XHold to adjust photo Ctrl+ZUndoEscUnpin

Bench reference

LPDDR4 nets are judged comparatively. In diode mode every DQ in a byte lane should read within a few counts of its seven siblings; the outlier is your damaged net. Same for the six CA lines, and the two legs of each DQS pair.

Rails are the exception: VDD1, VDD2 and VDDQ must each read a sane resistance to ground and never a dead short, and ZQ should read 240 Ω to VDDQ. A rail near zero ohms means a bridge, and the console will not power on at all.

Where to get a ballout

Tegra X1 / T210 — NVIDIA's own pinmux spreadsheet. The Jetson TX1 pinmux table from the Jetson Download Center lists Tegra X1 pin names together with their ball names; NVIDIA's own adaptation guide quotes SoC balls like E41, G43 and B42 straight out of it. It needs a free developer account, and it covers the muxable I/O — not the DRAM interface or the power and ground balls. Copy the ball-name column and the pin-name column into the import box and pick the net column when prompted.

Tegra X1 TRM. Also on developer.nvidia.com behind a free account, ~2977 pages, useful for what a pin actually does once you know its name.

Boardview for your exact revision. The only thing that gives you every ball including DRAM and power, matched to your HAC-CPU / HDH-CPU / HEG-CPU board. Export or copy the pin list for the SoC and paste it in. Match the revision exactly — positions are not transferable between Erista and Mariko boards.

Board layer scans from RetroSix and balika011's Erista layer viewer are the right companion for seeing where a trace physically runs once this tool tells you which net you lost.

About the SoC

Tegra X1 ball names are partly public: NVIDIA's Jetson TX1 pinmux spreadsheet lists pin names against ball names for the muxable I/O, and boardviews for specific Switch revisions cover everything else. What has never been published is a single authoritative full ballout — the DRAM interface and the power and ground balls are not in the pinmux table, and the complete map lives in the NDA-only Tegra X1 Embedded Datasheet.

The LPDDR4 map ships built in because five independent vendor datasheets agree on it row for row. The built-in SoC layouts are decoded from boardview files you supplied; their net names are anonymous except where a ball is wired to the LPDDR4 chips, which are named from the verified LPDDR4 map. Feed the import path the source you trust, and the tool tells you where its judgements come from.

For SoC and imported packages, criticality comes from redundancy over the netlist — a net on one ball is a single point of failure, a net on forty is a rail, partial rail loss graded by percentage.

Package & reballing (LPDDR4)

Standard	JEDEC MO-311, 200-ball FBGA
Pitch	0.80 mm cols × 0.65 mm rows
Ball Ø	0.30 mm ±0.05
Body	10 × 14.5 mm or 10 × 15 mm
Grid	22 × 12 positions; cols 6–7 and rows L–M depopulated

Both gutters are real, which is why the map draws as four blocks. A stencil must match this exact pattern — a solid 200-ball stencil without the gutters will bridge balls.

Switch notes

Every Switch carries two of these chips, each x32 with two independent 16-bit channels, forming the Tegra's 64-bit bus. There is no narrow-bus fallback — lose anything on either chip and memory training fails.

Identify your RAM by its marking. Samsung K4F… is LPDDR4, K4U… is LPDDR4X. Micron MT53B vs MT53E. SK hynix LPDDR4X parts end in …X. LPDDR4X runs its I/O rail at 0.6 V and is not required to tolerate 1.1 V.

The DRAM profile is selected from a fuse-burned DRAM ID, so a donor chip generally has to match the original vendor part or training will not complete even with perfect soldering.

Ballout cross-checked against Micron MT53B512M32D2, ISSI IS43LQ16256A, Rayson RS512M32LO4D1BDS, Zetta ZD53D16GA062FA and ICMAX IMH512M32H2D2ENA; behaviour from JESD209-4 and the LPDDR4X addendum.

Import a ballout stays in this browser